From www@isc.org Thu Feb 16 14:12:05 2017 MIME-Version: 1.0 X-Spam-Status: No, score=-3.3 required=5.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,RP_MATCHES_RCVD,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.0 X-Mailer: PHPMailer 5.2.22 (https://github.com/PHPMailer/PHPMailer) content-type: text/plain; charset="utf-8" Message-ID: <5880f661bc481144971de03d458003da@www.isc.org> Received: from mx.pao1.isc.org (mx.pao1.isc.org [IPv6:2001:4f8:0:2::2b]) by bugs.isc.org (Postfix) with ESMTP id 9329C71B5A8 for ; Thu, 16 Feb 2017 14:12:04 +0000 (UTC) Received: from iscwebprod.isc.org (iscwebprod.isc.org [IPv6:2001:4f8:1:d::16]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx.pao1.isc.org (Postfix) with ESMTPS id 3781D3493E2 for ; Thu, 16 Feb 2017 14:12:02 +0000 (UTC) Received: from www (uid 80) (envelope-from www@iscwebprod.isc.org) id 7b7d0b by iscwebprod.isc.org (DragonFly Mail Agent v0.11); Thu, 16 Feb 2017 14:12:01 +0000 Delivered-To: bind9-bugs@bugs.isc.org Subject: 9.10.4 - BIND occasionally hangs on MIPS based systems Return-Path: X-Original-To: bind9-bugs@bugs.isc.org Date: Thu, 16 Feb 2017 14:12:01 +0000 X-Wpcf7-Content-Type: text/plain X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mx.pao1.isc.org X-PHP-Originating-Script: 20001:class-phpmailer.php To: bind-bugs@isc.org From: "James Cowgill" X-RT-Original-Encoding: utf-8 X-RT-Interface: Email Content-Length: 1399 Bug Report from www.isc.org: Name: James Cowgill Email: jcowgill@debian.org Software Version: 9.10.4 OS: Debian Unstable Subject:BIND occasionally hangs on MIPS based systems Bug Detail =========== Originally reported here: https://bugs.debian.org/778720 There is a bug in the MIPS atomics implementation which can cause BIND to hang on MIPS. The patch to fix it is below. Please can you apply it. Thanks, James ========================== Subject: [PATCH] Add earlyclobber constraint in isc_atomic_cmpxchg() on mips The tmp register constraint should be earlyclobber ("=&r") because the other two registers (%3 and %4) will be read again after tmp (%2) is written if the code loops around. At the moment, GCC could make tmp and cmpval/val refer to the same register. --- lib/isc/mips/include/isc/atomic.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/isc/mips/include/isc/atomic.h b/lib/isc/mips/include/isc/atomic.h index e3657d7..13b5cff 100644 --- a/lib/isc/mips/include/isc/atomic.h +++ b/lib/isc/mips/include/isc/atomic.h @@ -79,7 +79,7 @@ isc_atomic_cmpxchg(isc_int32_t *p, int cmpval, int val) { " beqz %2, 1b \n" "2: move %0, $1 \n" " .set pop \n" - : "=&r"(orig), "+R" (*p), "=r" (tmp) + : "=&r"(orig), "+R" (*p), "=&r" (tmp) : "r"(cmpval), "r"(val) : "memory"); -- 2.5.1 --- This email was received through isc.org Bug Submission Form