| Subject: | 9.10.4 - BIND occasionally hangs on MIPS based systems |
| Date: | Thu, 16 Feb 2017 14:12:01 +0000 |
| To: | bind-bugs@isc.org |
| From: | "James Cowgill" <jcowgill@debian.org> |
Bug Report from www.isc.org:
Name: James Cowgill
Email: jcowgill@debian.org
Software Version: 9.10.4
OS: Debian Unstable
Subject:BIND occasionally hangs on MIPS based systems
Bug Detail
===========
Originally reported here: https://bugs.debian.org/778720
There is a bug in the MIPS atomics implementation which can cause BIND to hang on MIPS. The patch to fix it is below. Please can you apply it.
Thanks,
James
==========================
Subject: [PATCH] Add earlyclobber constraint in isc_atomic_cmpxchg() on mips
The tmp register constraint should be earlyclobber ("=&r") because
the other two registers (%3 and %4) will be read again after tmp
(%2) is written if the code loops around. At the moment, GCC could
make tmp and cmpval/val refer to the same register.
---
lib/isc/mips/include/isc/atomic.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/lib/isc/mips/include/isc/atomic.h b/lib/isc/mips/include/isc/atomic.h
index e3657d7..13b5cff 100644
--- a/lib/isc/mips/include/isc/atomic.h
+++ b/lib/isc/mips/include/isc/atomic.h
@@ -79,7 +79,7 @@ isc_atomic_cmpxchg(isc_int32_t *p, int cmpval, int val) {
" beqz %2, 1b \n"
"2: move %0, $1 \n"
" .set pop \n"
- : "=&r"(orig), "+R" (*p), "=r" (tmp)
+ : "=&r"(orig), "+R" (*p), "=&r" (tmp)
: "r"(cmpval), "r"(val)
: "memory");
--
2.5.1
---
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